BALD Engineering News Blog

BALD Engineering News Blog

About the Blog

Probably The Best ALD news blog. Covering new and old developments in Atomic Layer Deposition and Technology. From BALD Engineering:

jonas.sundqvist@baldengineering.com

http://www.baldengineering.com

Silicon capacitors: a new solution for decoupling applications

CapacitorPosted by Jonas 2014-01-22 10:43:02

EE Times Europe reports on Silicon Capacitors as new solutions for decoupling applications.


"As consumers are eager to get the most cutting-edge products, manufacturers have to adapt their technologies and continue to drive innovations to offer the most advanced electronic equipment.

Two key features must often be considered for electronic devices: size and performance. In order to anticipate the demand for more miniaturization and signal integrity over a wide range of frequencies in the decoupling applications, IPDiA adds to its silicon passive component library some ultra low ESR/ESL structures, in low profile form factor. These new silicon capacitors enable to drastically decrease the overall impedance and offer the best solution for decoupling performances up to 10 GHz frequency range."


A Mosaïc PICS capacitor design that can be embedded in a PCB.

Read the full article on page 32 of our January digital edition or download the PDF of this article directly here

Fraunhofer IPMS-CNT is developing new materials and processes for future generations of PICS in the EU project PICS for IPDIA together with CEA/Leti, Sentech and Picosun. Read more in a previous blog post here.







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PICS - A EU project to develop innovative Atomic Layer Deposition materials and tools for high density 3D integrated capacitors

CapacitorPosted by Jonas 2014-01-19 13:24:45

PICS - A EU project to develop innovative Atomic Layer Deposition materials and tools for high density 3D integrated capacitors

GRENOBLE and CAEN, France – Oct. 23, 2013 –CEA-Leti, Fraunhofer CNT and three European SMEs, IPDiA, Picosun and SENTECH Instruments, have launched a project to industrialize 3D integrated capacitors with world-record density.

Thetwo-year EU-funded PICS project is designed to develop a disruptive technology that results in a new worldrecord for integrated capacitor densities (over 500nF/mm2) combined with higher breakdown voltages. It will strengthen the SME partners’ position in several markets, such as automotive, medical and lighting, by offering an even higher integration level and more miniaturization.

The fast development of applications based on smart and miniaturized sensors in aerospace, medical, lighting and automotive domains has increasingly linked requirements of electronic modules to higher integration levels and miniaturization (to increase the functionality combination and complexity within a single package). At the same time, reliability and robustness are required to ensure long operation and placement of the sensors as close as possible to the “hottest” areas for efficient monitoring. For these applications, passive components are no longer commodities. Capacitors are indeed key components in electronic modules, and high-capacitance density is required to optimize – among other performance requirements – power-supply and high decoupling capabilities. Dramatically improved capacitance density also is required because of package shrink.

IPDiA has for many years developed an integrated capacitors technology thatout performs current technologies (e.g. tantalum capacitors) in terms of stability in temperature, voltage, aging and reliability. Now, a technological solution is needed to achieve higher capacitance densities, reduce power consumption and improve reliability. The key enabling technology chosen to bridge this technological gap is atomic layer deposition (ALD) that allows an impressive quality of dielectric.


Picture 1: Prototype of medical pills integrating temperature sensor and RF transceiver
Picture 2: 3D trench capacitors integrated into Silicon

The PICS project consortium will address all related technological challenges and setup a cost-effective industrial solution. Picosun will develop ALD tools adapted to IPDiA’s 3D trench capacitors. SENTECH Instruments will provide a new solution to more accurately etch high-K dielectric materials. CEA-Leti and Fraunhofer CNT will help the SMEs to create innovative technological solutions in order to improve their competitiveness and gain market share. Finally, IPDiA will manage the industrialization of these processes.

http://www.fp7-pics.eu

Dresden, Germany and Espoo, Finland, October 25, 2013 – Picosun Oy, the leading Atomic Layer Deposition (ALD)equipment manufacturer, provides novel batch ALD processes for fast, cost-efficient mass production of next generation 3D capacitors.

High power density 3D capacitor technology, which is suitable for storing and handling largequantities of energy, is utilized for example in pacemakers and other implantable medical devices, electric cars, and more and more efficient memories for computers and mobile devices. To realize these applications, power consumption, long-term stability, and general reliability of the capacitors and other related electronic components need improvement and their footprint substantial reduction.

Advanced, innovative ALD structures are in a central role when addressing these challenges and Picosun, as the leading supplier of mature batch ALD technology, is a natural choice for providing both ALD tools and processes for the capacitor manufacturing. With its demonstrated, optimized and production-proven ALD processes, Picosun is solidifying its position as the technological leader in the future 3D capacitor market.

“Picosun is the only company offering mature ALD batch equipment that can run stand alone or be clustered using a vacuum robot enabling a production ramp in a cost-efficient way. We aim at transferring our proven high-k capacitor material and process knowledge to an ALD batch system from Picosun and thereby improving cost-of-ownership for applications employing thicker high-k for high voltage applications. Such an offering is not available at the market today,” comments Dr. Jonas Sundqvist, group leader of high-k devices at Fraunhofer CNT, Germany. Fraunhofer CNT, a top European research center for micro- and nanoelectronics is one of Picosun’s collaboration partners in the EU 7th Framework Program project PICS (“Development of innovative ALD materials and tools for high density 3D integrated capacitors”, http://www.fp7-pics.eu/), a part of which the work for the next generation 3D capacitor production upscaling is.

Picosun’s world leading ALD technology enables industrial leap into the future by novel, cuttingedge coating solutions, with four decades of pioneering, groundbreaking expertise in the field. Today, PICOSUN™ ALD systems are in daily production use in numerous prominent industries around the globe. Picosun is based in Finland, it has its subsidiaries in USA and Singapore, and world-wide sales and support network.

http://www.picosun.com/









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Energy Storage on Chip Integrated Supercapacitors

CapacitorPosted by Jonas 2014-01-12 15:42:30

[From Fraunhofer IPMS-CNT Web www.cnt.fraunhofer.de] The progressive miniaturization of electronic devices such as of smartphones or sensors for medical, industrial and automotive applications requires smaller substrates. This drives amongst others the integration and scaling of space consuming external passive components for buffering and decoupling purposes on chip (SoC) or package (SiP) level. Simultaneously, extremely high capacitances are needed. The main parameters to increase the capacitance are on the one side the choice of an isolator material with high dielectric constant. Several high-k materials like HfO2, ZrO2 or Ta2O5 based systems are under investigation at the Fraunhofer IPMS-CNT .

Intensive material tuning is necessary to meet the electrical requirements for capacitor applications with respect to capacitance density and linearity, leakage current and reliability. While doing this, the capacitor area has to be as large as possible andthat can be achieved by 3D integration of high aspect ratio (AR) structures.

a) SEM cross section of a trench array with AR 13:1 filled with MIM stack and b) top down micrograph of Si trench array after silicon etch.

c) TEM micrograph of a MIM stack

The Fraunhofer IPMS-CNT has developed Si-integrated high-density capacitors based on 300 mm wafer technology aiming to buffer capacitor applications. A simplified patterning scheme using e-beam lithography and high technology dry etch processes provides structures with large aspect ratio in a high package density (Figure 1a and 1b). The used capacitor stack is based on a metalinsulator-metal (MIM) structure built from Al-doped ZrO2 as dielectric and TiN electrodes. All materials are deposited by atomic layer deposition to reach highly conformal step coverage in the large aspect ratio structures (Figure 1c). The electrical characteristics show very low leakage current densities normalized for a capacitor of 1 μF. Thereby, the capacitance is stable over the voltage region with a deviation smaller than 3 %.

The temperature stability is below 5 %. These values are significantly lower compared to common ceramic capacitors. The good electrical results are complemented by a reliability over 10 years. The maximum capacitance reached for the AR of 6:1 (Gen2) lies around 100 nF/mm2 for the material system which is adapted to an operation voltage of 3 V. This is a significant increase compared to planar capacitors (Gen1).. By increasing the AR to 13:1 (Gen3) a capacitance enhancement to 220 nF/mm2 could be achieved.

The Fraunhofer IPMS-CNT forces also an up-scaling of the 3D capacitors (Gen4-5) either by an improved etch-process or by using materials with higher dielectric constant. The outlook predicts integrated capacitors of 1 μF.

Further Information can be find in this excellent pape by Wenke Weinreich et al

High-density capacitors for SiP and SoC applications based on three-dimensional integrated metal-isolator-metal structures, Weinreich, W., Rudolph, M. ; Koch, J. ;Paul, J. ; Seidel, K. ; Riedel, S. ; Sundqvist, J. ; Steidel, K. ; Gutsch, M. ;Beyer, V. ;Hohle, C. Bus. Unit Fraunhofer Center Nanoeletronic Technol., Fraunhofer Inst. of Photonic Microsyst., Dresden, Germany, 2013 IEEE International Conference onIntegrated Circuit Design









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