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Probably The Best ALD news blog. Covering new and old developments in Atomic Layer Deposition and Technology. From BALD Engineering:

Iphone 5s - The Apple A7 processor fabed by Samsung using 28nm low-power, gate-first, HKMG process technology

HKMGPosted by Jonas 2014-01-21 21:58:26

[The following comes from a Blog by EETimes and other sources as indicated, the original Chipworks report]

The Apple A7 processor used inside the iPhone 5s has earlier been analyzed by Chipworks (Inside the iPhone 5s] and now the interesting part has become available - The Front End cross sections of the NMOS and PMOS.
Apple's A7, a 64-bit system-on-chip ARM. AnandTech has published a review here. (Source: Chipworks)

From the blog:
"The A7 is Apple’s first 28nm device. The process technology is broadly similar to that used at 32nm, with an ~10% shrink of the contacted gate pitch to 120nm. The PMOS and NMOS transistors are easily distinguished due to marked differences in the transistor structure.

The NMOS transistors feature an NMOS work function metal gate (MG) deposited onto the high-k (HK) gate dielectric, which is composed of hafnium oxide deposited over a thin layer of silicon dioxide. The process is described as gate-first since the silicided polysilicon gate is deposited after the HKMG gate stack has been formed.

The main distinguishing features of the PMOS transistors are the presence of a SiGe channel beneath the PMOS gates and a separate PMOS work function metal deposited over the HK dielectric stack.

The NMOS MG layer is present over the PMOS MG layer, indicating that the PMOS transistors were formed first in the process flow. This NMOS MG layer would have no effect on the electrical characteristics of the PMOS transistor, although it may serve as a barrier to protect the PMOS MG layer during the polysilicon deposition process step. There are minor differences in the shape of the sidewall spacer structure (SWS) for the PMOS as compared to the NMOS transistors, while both transistor types are sealed with the same contact etch stop layer (CESL)."

PMOS (left) and NMOS (right) from Apple's A7 (Source: Chipworks)

Samsung information on 32/28nm Low-Power High-K Metal Gate Logic can be find here. Accoring to Sasmung, the Samsung Austin Semiconductor (SAS) is one of the most advanced semiconductor manufacturing facilities in the United States., SAS is the only semiconductor manufacturing plant located outside of Korea. SAS manufactures logic components for digital services, personal computers, mobile phones, workstations and servers and has been operationg since 1997.

Here is an interesting video from the Austin Chamber of commerce explaining the The Austin Tech Economy around Samsung and the University of Texas.

Samsung Electronics' S2 Austin, Tex. fab: The 28 nm fab is located near facilities for Texas Instruments and Apple. [Image Source: Let's Go Digital] According to Wikipedia this fab produces 40.000 Wafers per Month, but that was some time ago (2011)

Check out the Fab on Google Maps!

As far as I know Samsung is producing their Apple 28 nm chips in the Austin Texas Fab. There are a lot of rumours out there and it will for sure be interesting to see if Apple will also keep on producing chips on US soil while technology is scaling down. Next big step for Apple is FinFET technology and then for sure TSMC is strong - but what about Intel? I assume all big players are doing their best to get thos orders in the future. To me it seem like a completely open race.

Back to reality - We can assume that the high-k gate oxide, HfO2 in this case as reported by Chipworks has been deposited by ALD or CVD. Since it is gate first technology it is possible to allow a higher thermal budget for depositing the gate oxide so you can get away with CVD. The reason is that the sourc/drain contacts are formed at a later stage in the high-k first process flow. If high-k last is used, then there is a restricion in thermal budget to keep the NiSi contacts alive and the ALD is used. Intel and many foundries uses the ASM Pulsar 3000 chambers for gate oxide. For all you ALD geeks out there, there is a very good page for Pulsar 3000 Lovers.

Check it out - The Switch is on!

Above, The Polygon 8300 platform configured with 2 Pulsar 3000 ALD process modules. A commonly used platform in the industry to produce high performance high-k for high performance transistors (

By using the same ALD chamber and by tweeking the HfO2 gate oxide ALD recipe a bit, making it thicker and adding a bit of dopant the high-k can be made ferroelectric and be integreated into a 28 nm device in a similar way as desribed above as a FeFET. Read more about that exiting technology here :

Exiting? If you want to come and have a look at one of these fantasic ALD chambers in action - poof-poof-poof-pooof - do not hesitate to schedule a visit at Fraunhofer IPMS-CNT next time you´re in Dresden! Why not conme and visit us at the Industry Day 6th of February?

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