BALD Engineering News Blog

BALD Engineering News Blog

About the Blog

Probably The Best ALD news blog. Covering new and old developments in Atomic Layer Deposition and Technology. From BALD Engineering:

jonas.sundqvist@baldengineering.com

http://www.baldengineering.com

A CMOS-compatible and highly scalable approach to future ferroelectric memory

Emerging MemoryPosted by Jonas 2014-02-11 23:25:22

Even though researched for several decades, the ferroelectric fi eld effect transistor (FeFET) based on traditional perovskitebased ferroelectrics like PZT or SBT still has fundamental shortcomings. Its potential, however, remains unchallenged.
Like for DRAM, FRAM data storage depends on charge per area and therfore 3D scaling is a must. At IEDM 2006 (Koo et al, above) an attempt to scale FRAM in 3D was presented, as can be seen no charge gain per cell is made since no ferroelectric material (PZT of ferroelctric phase) is depoited on the sidewalls of the trench. In addition, the physical thickness of PZT limits the trench diameter.[1]


Unlike the current-based STT-MRAM, RRAM, PCRAM and Flash technologies the ferroelectric approach is based on a fi eld effect and consumes the lowest power during switching. Scalability and manufacturability on the other hand still remain a major issue when utilizing perovskite-based ferroelectrics.

TEM micrographs of the TiN/Si:HfO2/SiO2/Si gate stack and the complete FeFET device showing steep sidewall angles as a result of extensive RIE development.[2]

Recently however, a method to engineer ferroelectricity in the well-known and fully CMOS-compatible HfO2 based dielectrics was discovered. With this ability at hand a consortium of researchers from GLOBALFOUNDRIES, NaMLab gGmbH, and Fraunhofer IPMS-CNT were able to demonstrate that the two order of magnitude scaling gap, prevailing ever since the introduction of FeFETs, is fi nally closed at the 28 nm technology node. As indicated in Figure 1 the world´s most aggressively scaled FeFETs were successfully fabricated using ferroelectric Si:HfO2 in a 28 nm HKMG stack (TiN/Si:HfO2/SiO2/Si). Excellent 300 mm yield, switching in the nanosecond range, and 10-year retention were achieved with fi rst silicon. The consortium further demonstrated endurance characteristics matching demands of current NVMs utilizing wear leveling.

From VLSI 2012 presentation [2] - a comparasion of HfO2 based FeFET with previously published FeFET work based on PZT and similar materials. [presentation available thru Research Gate]

As prensented on IEDM 2013 by J. Müller et al, the implementation of FE-HfO2 into device structures similar to state of the art DRAM storage capacitors or HKMG transistors yields highly competitive 1T/1C and 1T FRAM solutions. Excellent retention and fast switching has been demonstrated. The improvement of the endurance characteristic of the material remains an open challenge for broadening the scope of potential memory applications. [1]


From IEDM 2013 abstratct [1] The prospects of FE-HfO2-based capacitors are contrasted to state of the art FRAM (table). STEM cross sections of an Al:HfO2–based trench capacitor array (#30k, 1.6 μm depth). P-E-Hysteresis reveal a stable Pr of 14 μC/cm2 (planar: 15 μC/cm2) in 3D-cpacitors enabling a Pr of 150 μC/cm2 in planar area projection.

[1] Ferroelectric Hafnium Oxide A CMOS-compatible and highly scalable approach to future ferroelectric memories
[Free download by Fraunhofer CNT]
J. Müller, T.S. Böscke, S. Müller, E. Yurchuk, P. Polakowski, J. Paul, D. Martin, T. Schenk, K. Khullar, A. Kersch, W. Weinreich, S. Riedel, K. Seidel, A. Kumar, T.M. Arruda, S.V. Kalinin, T. Schlösser, R. Boschke, R. van Bentum, U. Schröder, T. Mikolajick

Proceedings of International Electron Devices Meeting 2013, (2013) 280-283

[2] Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG

J Müller, E Yurchuk, T Schlösser, J Paul, R Hoffmann, S Müller, D Martin, S Slesazeck, P Polakowski, J Sundqvist, M Czernohorsky, K Seidel, P Kücher, R Böschke, M Trentzsch, K Gebauer, U Schröder, T Mikolajick

Proceeding of Symposium on VLSI Technology (VLSIT) 2012; 06/2012


[post will be updated with more publications on this topic]

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ARM is evaluating CeRAM technology for embedded NVM

Emerging MemoryPosted by Jonas 2014-02-09 13:56:17
ARM is evaluating CeRAM - correlated electron random access memory - technology for embedded NVM according to a recent statment from Symetrix:

ARM is evaluating CeRAM technology as part of its strategy in embedded nonvolatile memory offerings and their discussions with Symetrix started over three months ago. Symetrix will provide its technology and the results from Symetrix programs ongoing at the University of Texas (Dallas) and the University of Colorado (Colorado Springs) to chip foundries engaged by ARM. Other chip companies are also working with Symetrix under similar terms.


EE Times also reported on this and CeRAM technology here: CeRAM Memory Gets ARM's Attention:

"CeRAM is based on a transition metal oxide, in this case nickel oxide (NiO). The premise is that, by cleaning up NiO through a suitable doping technique, it is possible to obtain electrically conducting NiO that can make very rapid, reversible, nonvolatile bulk transitions between its electrically insulating and conducting states. In the past, these transitions were possible only at a high pressure and temperature, but they now can be achieved at room temperature with low switching voltages and currents. Key to the operation is a reversible metal-to-insulator transition (MIT) that has its roots in the work of Sir Nevill Mott and John Hubbard. "

Here is a descriptive presentation from Symetrix that goes into detail on CeRAM and compares it to the more mainbstream ReRAM technology. In short:

1) CeRAM vs. Filament Technologies (ReRAM) according to Symetrix

• Control of material properties and proper device architecture are fundamental to this new paradigm. Evidence? No filament formation. (No electroforming)

• The CeRAM resistor is designed to exploit materials properties, surface properties, switching mechanism (endurance) and memory mechanism (retention).

• Optimizing CeRAM is a different science than building the perfect filament.

Unlike ReRAM, CeRAM is resistive memory which uses the same transition metal oxide (TMO), such as NiO, but strands are not used and electroplating. Instead CeRAM-memory quantum correlation effects observed positions of electrons, where it got its name. In the structure of the active region is allocated CeRAM TMO, which separates the two conductive layers TMO, whereas in the transition metal oxide ReRAM occupies entire domain between the metal layers.

2) CeRAM STATUS according to Symetrix:

THEORY: Confirmed with empirical results DONE

MATERIALS: Doping any TMO with any extrinsic ligand PATENTED

PROCESS: Create and isolate thin (5 nm) active region by simple spin-on or ALD PATENT FILED

ARCHITECTURE: Array only (no pass gate) PATENTED

3-D (STACKING) With only silicon friendly materials IN PROCESS

FPGA Architecture PATENT FILED

Further References on CeRAM:

Patents:
16 Patents by Symetrix (as assignee) on "correlated electron memory" as returned from Google Patent search.

Publications on CeRAM:

“A non-filamentary model for unipolar switching transition metal oxide resistance random access memories”, Kan-Hao Xue, Carlos Paz De Araujo, Jolanta Celinska, and Christopher McWilliams, J. Appl. Phys. 109, 091602 (2011)

“Material and process optimization of correlated electron random access memories”, Jolanta Celinska, Christopher McWilliams, Carlos Paz De Araujo, and Kan-Hao Xue, J. Appl. Phys. 109, 091603 (2011)

“Device characterization of correlated electron random access memories”, Christopher McWilliams, Jolanta Celinska, Carlos Araujo, and Kan-Hao Xue, J. Appl. Phys. 109, 091608 (2011)

“Operating Current Reduction in Nickel Oxide Correlated Electron Random Access Memories (CeRAMs) through Controlled fabrication Processes”, Jolanta Celinska, Christopher McWilliams, Carlos Paz De Araujo, and Kan-Hao Xue, Integrated Ferroelectrics, 124, 105-111 (2011)

“Re-Programmable Antifuse FPGA Utilizing Resistive CERAM Elements”, Christopher McWilliams, Carlos Paz De Araujo, Jolanta Celinska, and Kan-Hao Xue, Integrated Ferroelectrics, 124, 97-104 (2011)

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PVD Free processes used for future emerging memory technologies

Emerging MemoryPosted by Jonas 2014-02-08 12:41:35
This week at the Fraunhofer IPMS-CNT Industry Day, Malgorzata Jurczak, Director Emerging Memory Devices - IMEC, stated that "PVD-free processes (ALD/CVD) are needed for Emerging Memory" To visualize this in the case of 3D NAND there is a recent blog post (SemiMD.com) on the topic - and yes obviously PVD and also not CVD can´t be an option for these highly scaled 3D architectures. Below is a brief snapshot [complete story here]

"The current iteration of NAND flash technology, 2D – or planar – NAND, is reaching its limits. In August 2013, South Korean consumer electronics brand Samsung announced the launch of its 3D NAND storage technology, in the form of a 24-layer, 128 GB chip. In 2014, memory chipmakers Micron and also SK Hynix will follow suit, heralding the arrival of a much-anticipated and debated technology during various industry conferences in recent years. Other companies, including Sandisk, are all working on 3D NAND flash technology." as reported by Sara Ver-Bruggen, contributing editor at Semiconductor Manufacturing and Design.

“Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic-layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer, which is also true of the layers that are deposited on the walls of the hole,” according to Handy. [Jim Handy from Objective Analysis, who is writing aboute NAND and 3D NAND in the Memory Guy Blog]


3D NAND manufacturing considerations and challenges - Staircase etching requires very precise contact landing and the ALD process has to be applied with a constant thickness in 3D across the whole 300mm wafer. Obviously PVD or CVD is not an option at all. These staircase contacts could have an 60:1 aspect ratio.


Chuck Dennison, Senior Director Process Integration, from Micron, explained for 3DNAND “There is a lot planarization, you are etching very high aspect ratio contacts where you need to be very controlled, in terms of how you define your control and CD uniformity. Then there are a lot of additional modules requiring ALD deposition. So we think that there is a lot of opportunity to utilize our DRAM expertise.”

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