BALD Engeneering News Blog has moved to Blogspot
Carolyn R. Ellinger and Shelby F. Nelson
Chem. Mater. January 30, 2014 (Web)
Spatial atomic layer deposition (SALD) is gaining traction in the thin film electronics field because of its ability to produce quality films at a fraction of the time typically associated with ALD processes. Here, we explore the process space for the fabrication of thin film patterned-by-printing electronics using the combination of SALD and selective area patterning. First, a study of SALD growth conditions for the three primary components of our metal oxide thin film electronics, namely alumina (Al2O3) dielectric, zinc oxide (ZnO) semiconductor, and aluminum doped ZnO (AZO) conductor, provides insight into the potential trade-offs in performance, substrate latitude (temperature), and process speed. At constant precursor partial pressures, the precursor exposure times and substrate temperatures were varied from 25 to 400 ms and from 100 to 300 °C, respectively. The very short gas exposure and purge times obtainable only with a spatial implementation of ALD are shown always to be advantageous for throughput and process speed, even though growth is far from the “ideal” ALD condition of saturated monolayer growth. Using the same range of process conditions, we evaluated the ability of very thin layers of poly(vinyl pyrrolidone) (PVP) to inhibit film growth. We demonstrate that PVP sufficiently inhibits the growth of all three materials at temperatures at or above 150 °C to usefully pattern high-quality electronic devices. Additionally, we found that very thin layers of PVP are most effective at higher temperatures and fast ALD cycles. Thus, faster SALD cycles are advantageous from both throughput and patterning performance perspectives.
Even though researched for several decades, the ferroelectric fi eld effect transistor (FeFET) based on traditional perovskitebased ferroelectrics like PZT or SBT still has fundamental shortcomings. Its potential, however, remains unchallenged.
Like for DRAM, FRAM data storage depends on charge per area and therfore 3D scaling is a must. At IEDM 2006 (Koo et al, above) an attempt to scale FRAM in 3D was presented, as can be seen no charge gain per cell is made since no ferroelectric material (PZT of ferroelctric phase) is depoited on the sidewalls of the trench. In addition, the physical thickness of PZT limits the trench diameter.
Unlike the current-based STT-MRAM, RRAM, PCRAM and Flash technologies the ferroelectric approach is based on a fi eld effect and consumes the lowest power during switching. Scalability and manufacturability on the other hand still remain a major issue when utilizing perovskite-based ferroelectrics.
TEM micrographs of the TiN/Si:HfO2/SiO2/Si gate stack and the complete FeFET device showing steep sidewall angles as a result of extensive RIE development.
Recently however, a method to engineer ferroelectricity in the well-known and fully CMOS-compatible HfO2 based dielectrics was discovered. With this ability at hand a consortium of researchers from GLOBALFOUNDRIES, NaMLab gGmbH, and Fraunhofer IPMS-CNT were able to demonstrate that the two order of magnitude scaling gap, prevailing ever since the introduction of FeFETs, is fi nally closed at the 28 nm technology node. As indicated in Figure 1 the world´s most aggressively scaled FeFETs were successfully fabricated using ferroelectric Si:HfO2 in a 28 nm HKMG stack (TiN/Si:HfO2/SiO2/Si). Excellent 300 mm yield, switching in the nanosecond range, and 10-year retention were achieved with fi rst silicon. The consortium further demonstrated endurance characteristics matching demands of current NVMs utilizing wear leveling.
From VLSI 2012 presentation  - a comparasion of HfO2 based FeFET with previously published FeFET work based on PZT and similar materials. [presentation available thru Research Gate]
As prensented on IEDM 2013 by J. Müller et al, the implementation of FE-HfO2 into device structures similar to state of the art DRAM storage capacitors or HKMG transistors yields highly competitive 1T/1C and 1T FRAM solutions. Excellent retention and fast switching has been demonstrated. The improvement of the endurance characteristic of the material remains an open challenge for broadening the scope of potential memory applications. 
From IEDM 2013 abstratct  The prospects of FE-HfO2-based capacitors are contrasted to state of the art FRAM (table). STEM cross sections of an Al:HfO2–based trench capacitor array (#30k, 1.6 μm depth). P-E-Hysteresis reveal a stable Pr of 14 μC/cm2 (planar: 15 μC/cm2) in 3D-cpacitors enabling a Pr of 150 μC/cm2 in planar area projection.
 Ferroelectric Hafnium Oxide A CMOS-compatible and highly scalable approach to future ferroelectric memories
[Free download by Fraunhofer CNT]
J. Müller, T.S. Böscke, S. Müller, E. Yurchuk, P. Polakowski, J. Paul, D. Martin, T. Schenk, K. Khullar, A. Kersch, W. Weinreich, S. Riedel, K. Seidel, A. Kumar, T.M. Arruda, S.V. Kalinin, T. Schlösser, R. Boschke, R. van Bentum, U. Schröder, T. Mikolajick
Proceedings of International Electron Devices Meeting 2013, (2013) 280-283
 Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG
J Müller, E Yurchuk, T Schlösser, J Paul, R Hoffmann, S Müller, D Martin, S Slesazeck, P Polakowski, J Sundqvist, M Czernohorsky, K Seidel, P Kücher, R Böschke, M Trentzsch, K Gebauer, U Schröder, T Mikolajick
Proceeding of Symposium on VLSI Technology (VLSIT) 2012; 06/2012
[post will be updated with more publications on this topic]
• Control of material properties and proper device architecture are fundamental to this new paradigm. Evidence? No filament formation. (No electroforming)
• The CeRAM resistor is designed to exploit materials properties, surface properties, switching mechanism (endurance) and memory mechanism (retention).
• Optimizing CeRAM is a different science than building the perfect filament.
Unlike ReRAM, CeRAM is resistive memory which uses the same transition metal oxide (TMO), such as NiO, but strands are not used and electroplating. Instead CeRAM-memory quantum correlation effects observed positions of electrons, where it got its name. In the structure of the active region is allocated CeRAM TMO, which separates the two conductive layers TMO, whereas in the transition metal oxide ReRAM occupies entire domain between the metal layers.
2) CeRAM STATUS according to Symetrix:
THEORY: Confirmed with empirical results DONE
MATERIALS: Doping any TMO with any extrinsic ligand PATENTED
PROCESS: Create and isolate thin (5 nm) active region by simple spin-on or ALD PATENT FILED
ARCHITECTURE: Array only (no pass gate) PATENTED
3-D (STACKING) With only silicon friendly materials IN PROCESS
FPGA Architecture PATENT FILED
Further References on CeRAM:
16 Patents by Symetrix (as assignee) on "correlated electron memory" as returned from Google Patent search.
Publications on CeRAM:
“A non-filamentary model for unipolar switching transition metal oxide resistance random access memories”, Kan-Hao Xue, Carlos Paz De Araujo, Jolanta Celinska, and Christopher McWilliams, J. Appl. Phys. 109, 091602 (2011)
“Material and process optimization of correlated electron random access memories”, Jolanta Celinska, Christopher McWilliams, Carlos Paz De Araujo, and Kan-Hao Xue, J. Appl. Phys. 109, 091603 (2011)
“Device characterization of correlated electron random access memories”, Christopher McWilliams, Jolanta Celinska, Carlos Araujo, and Kan-Hao Xue, J. Appl. Phys. 109, 091608 (2011)
“Operating Current Reduction in Nickel Oxide Correlated Electron Random Access Memories (CeRAMs) through Controlled fabrication Processes”, Jolanta Celinska, Christopher McWilliams, Carlos Paz De Araujo, and Kan-Hao Xue, Integrated Ferroelectrics, 124, 105-111 (2011)
“Re-Programmable Antifuse FPGA Utilizing Resistive CERAM Elements”, Christopher McWilliams, Carlos Paz De Araujo, Jolanta Celinska, and Kan-Hao Xue, Integrated Ferroelectrics, 124, 97-104 (2011)
“Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic-layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer, which is also true of the layers that are deposited on the walls of the hole,” according to Handy. [Jim Handy from Objective Analysis, who is writing aboute NAND and 3D NAND in the Memory Guy Blog]
3D NAND manufacturing considerations and challenges - Staircase etching requires very precise contact landing and the ALD process has to be applied with a constant thickness in 3D across the whole 300mm wafer. Obviously PVD or CVD is not an option at all. These staircase contacts could have an 60:1 aspect ratio.
Chuck Dennison, Senior Director Process Integration, from Micron, explained for 3DNAND “There is a lot planarization, you are etching very high aspect ratio contacts where you need to be very controlled, in terms of how you define your control and CD uniformity. Then there are a lot of additional modules requiring ALD deposition. So we think that there is a lot of opportunity to utilize our DRAM expertise.”
Uniaxial compression test of a polymeric truss structure (right). Failure due to local buckling of diagonal struts under compressive load is followed by large plastic deformations and fracture. Before the collapse, bending of single struts due to processing-related predeformation (shrinking effects) also is observed. Uniaxial compression test of a polymeric truss structure (left) coated with 10 nm of [ALD] Al2O3. Local buckling of individual vertical compression bars leads to the immediate collapse of the whole structure. Only a little plastic deformation can be observed.
To enhance the strength-to-weight ratio of a material, one may try to either improve the strength or lower the density, or both. The lightest solid materials have a density in the range of 1,000 kg/m3; only cellular materials, such as technical foams, can reach considerably lower values. However, compared with corresponding bulk materials, their specific strength generally is significantly lower. Cellular topologies may be divided into bending- and stretching-dominated ones. Technical foams are structured randomly and behave in a bending-dominated way, which is less weight efficient, with respect to strength, than stretching-dominated behavior, such as in regular braced frameworks. Cancellous bone and other natural cellular solids have an optimized architecture. Their basic material is structured hierarchically and consists of nanometer-size elements, providing a benefit from size effects in the material strength. Designing cellular materials with a specific microarchitecture would allow one to exploit the structural advantages of stretching-dominated constructions as well as size-dependent strengthening effects. In this paper, we demonstrate that such materials may be fabricated. Applying 3D laser lithography, we produced and characterized micro-truss and -shell structures made from alumina–polymer composite. Size-dependent strengthening of alumina shells has been observed, particularly when applied with a characteristic thickness below 100 nm. The presented artificial cellular materials reach compressive strengths up to 280 MPa with densities well below 1,000 kg/m3.
The Tove Jansson collector coin will be issued on 7 February. It will be available on the Mint of Finland online shop and from distributors.
best known as the author of the Moomin books for children. The first such book,
The Moomins and the Great Flood, appeared in 1945, though it was the next two
books, Comet in Moominland and Finn Family Moomintroll, published in 1946 and
1948 respectively, that brought her fame. Tove Jansson was selected one time
previously as the main motif in the 2004 minting of a Finnish commemorative
coin, the €10 Tove Jansson and Finnish Children's Culture commemorative coin. [Wikipedia]
ALD:ed Tove Jansson €20 coin from Mint of Finland. The coins have been coated with nSILVER(R) from BENEQ to protect them from oxidation.
More information on the BENEQ nSILVER coating you can find here and below you can watch a Video on development of silver saving technology by University of Maryland using a BENEQ TSF 500 Batch ALD reactor.
Sentech (www.sentech.de) announces that "In good tradition
SENTECH is glad to announce its annual Plasma Seminar which takes place on
Thursday, February 27th, 2014 at SENTECH Instruments GmbH, Schwarzschildstraße
2, Berlin Adlershof.
As the global interest in Nanotechnology is growing, we want to get our participants introduced to new topics in fields of deposition and etching combined with recent examples. Invited speakers will focus on topics such as the deposition through ALD and PE-ALD, the etching of micro- and nanostructures in Si, the manufacturing of graphene films and the deposition of passivation and encapsulation films through IC PECVD and ALD. The whole Seminar Program can be downloaded here: Programme_SENTECH Plasma Seminar . If you want to participate please send this Registration for SENTECH`s Plasma Process Technology Seminar to: email@example.com
After the seminar there will be a presentation of the SENTECH application laboratories and its production facilities. The whole material of this seminar will be provided for all participants.
For further information don`t hesitate to contact us or call: +49 89 8979607-0"
On the forecast of ALD systems sales in 2014 he said "This year we’ll be probably in the range of 50 systems…” and he went on "… we hope to diversify more than we are today and hopefully outside the semiconductor industry and my objective is to move into the medical field and the MEMS area and sensors if we can.”
The complete transcript of the
call is available here: Seeking Alpha
For all ALD maniacs out there I can realy recomend to spend some time on Cambridge Nanotech´s web - it is realy informative : Cambridge Nanotech. Especially interesting is the Knowledge center with customer papers, tutorials an more. Earlier they used to have a very good Abstract database but I have not been able to locate that one since Ultratech bought them.
Here you can read more about their well known ALD systems:
Lab ALD - The Savannah http://www.cambridgenanotechald.com/thin-film-deposition.html
PEALD - The Fiji http://www.cambridgenanotechald.com/advanced-thin-films.html
Batch ALD - The Phoenix http://www.cambridgenanotechald.com/batch-ald-system.html
AVING NET reports that JUSUNG ENGINEERING(www.jseng.com) to introduce its semiconductor product including 'Space Divided Plasma System'(SDP), which features largely three functions which are 'ALD', 'CVD' and 'Treatment' for Nitridation, Oxidation and Doping. The system is capable to go through the process of ordinary PECVD, LPCVD and Defusion Furnishing, which can solve wafer damage problem by plasma.
Image from AVING NET - Jusung SDP - Space Divided Plasma System
SEMICON Korea 2014
▶ February 12(Wen) - 14(Fri), 2014
▶ Venue: Hall A, B, C, D 1F&3F, COEX, Seoul, Korea
▶ Program: Exhibition, SEMI Technology Symposium
▶ Program: Press Conference, imec Technology Forum, Keynote Speech, Executive Forum, SEMI Technology Symposium(STS), LED Korea Conference 2014.
▶ Organized by: SEMI (Semiconductor Equipment and Material International)
As reported by Seeking
Alpha - Lam Research Management Discusses Q2 2014 Results - Earnings Call
“In DRAM, the number of multi-patterning
steps more than doubles with the transition to 20-nanometer going from 3 or 4
in a mid-2x device to between 8 and 10 at 20-nanometer, with the same evidence
of upsize on number of passes. You should expect more specificity from Lam on
this in the coming quarters. This transition also presents growth opportunities for our deposition business. Many of the spacer-based, multi-patterning deposition steps can be done with batch variances today. However, customers are evaluating or starting to transition these steps to single wafer atomic layer deposition, or ALD tools, as the film conformality and uniformity requirements increased.”
Access the full transcript thru Seeking Alpha
Jan. 29, 2014 9:50 PM ET
"At the sub-14nm technology node, transistor performance will be highly sensitive to process variations, which can significantly impact current leakage and battery power loss. To give some perspective on the reality of the challenges, within the next 10 years, transistor gate dimensions are expected to be less than 50 atoms wide, and feature size variations will be measured in atoms, including contributions from surface roughness. Atomic layer processes are the most promising path for delivering the precision needed at this scale. Atomic layer deposition (ALD) has been in production for over a decade in the semiconductor manufacturing industry. However, it has been difficult making the etch counterpart — atomic layer etch (ALE) — productive enough for cost-effective manufacturing, and a commercially viable system has not been available. Here, we report on a plasma-enhanced ALE method using a commercial plasma reactor that provides atomic-level precision with process times that are suitable for high-volume device manufacturing."
EE Times Europe reports on Silicon Capacitors as new solutions for decoupling applications.
"As consumers are eager to get the most cutting-edge products, manufacturers have to adapt their technologies and continue to drive innovations to offer the most advanced electronic equipment.
Two key features must often be considered for electronic devices: size and performance. In order to anticipate the demand for more miniaturization and signal integrity over a wide range of frequencies in the decoupling applications, IPDiA adds to its silicon passive component library some ultra low ESR/ESL structures, in low profile form factor. These new silicon capacitors enable to drastically decrease the overall impedance and offer the best solution for decoupling performances up to 10 GHz frequency range."
A Mosaïc PICS capacitor design that can be embedded in a PCB.
Read the full article on page 32 of our January digital edition or download the PDF of this article directly herehere.
From the blog:
"The A7 is Apple’s first 28nm device. The process technology is broadly similar to that used at 32nm, with an ~10% shrink of the contacted gate pitch to 120nm. The PMOS and NMOS transistors are easily distinguished due to marked differences in the transistor structure.
The NMOS transistors feature an NMOS work function metal gate (MG) deposited onto the high-k (HK) gate dielectric, which is composed of hafnium oxide deposited over a thin layer of silicon dioxide. The process is described as gate-first since the silicided polysilicon gate is deposited after the HKMG gate stack has been formed.
The main distinguishing features of the PMOS transistors are the presence of a SiGe channel beneath the PMOS gates and a separate PMOS work function metal deposited over the HK dielectric stack.
The NMOS MG layer is present over the PMOS MG layer, indicating that the PMOS transistors were formed first in the process flow. This NMOS MG layer would have no effect on the electrical characteristics of the PMOS transistor, although it may serve as a barrier to protect the PMOS MG layer during the polysilicon deposition process step. There are minor differences in the shape of the sidewall spacer structure (SWS) for the PMOS as compared to the NMOS transistors, while both transistor types are sealed with the same contact etch stop layer (CESL)."
Dresden, Jan 20, 2014
For three-and-a-half years, five research institutions and two industrial companies have been working with in the scope of the European joint research project »TACO« on the development of a new kind of 3D-camera system that should allow robots to perform more demanding tasks. The Fraunhofer Institute for Photonic Microsystems IPMS in Dresden hereby contributed a novel MEMS scan technology as a key hardware component. This allows »relevant« objects in the surroundings to be detected with a higher resolution, similar to human vision , without having to increase the volume of data. At the Photonics West in San Francisco from the fourth to the sixth of February 2014, the Fraunhofer IPMS will be presenting the complete camera system for the first time as a fully-functional prototype to a broad professional public.
(a) an annular antenna disposed at a margin of the contact lens, wherein the antenna is configured to receive a power signal;
(b) a light-emitting diode (LED) configured to transmit a data signal;
(c) a biosensor module configured to measure a characteristic of the user's eye, the biosensor module comprising an electromechanical sensor comprising:
(i) a working electrode;
(ii) a counter electrode;
(iii) a reference electrode; and
(iv) a biosensor circuit configured to measure the voltage of the working electrode, the counter electrode, and the reference electrode, and to transmit a biosensor signal
Substrate biasing has been implemented in a remote plasma atomic layer deposition (ALD) reactor, enabling control of the ion energy up to 260 eV. For TiO2 films deposited from Ti(CpMe)(NMe2)3 and O2 plasma it is demonstrated that the crystalline phase can be tailored by tuning the ion energy. Rutile TiO2was obtained at 200 and 300°C, typically yielding amorphous and anatase films without biasing. Aspects such as film mass density, [O]/[Ti] ratio and growth per cycle under biased conditions are addressed. The results demonstrate that substrate biasing is a viable method for ALD to tailor ultra-thin film properties.
Beneq reported on Wednesday, December 11, that Beneq received a special commercialization breakthrough award from Tekes, the Finnish funding agency for technology and innovation, as part of its six-year-long Functional Materials program. The goal of the program was to promote the development of application-focused materials and processes, as well as to raise foreign investor awareness of Finland’s exceptionally high level of material expertise.
Beneq was selected for the Commercialization Breakthrough award thanks to the company’s outstanding work on two particular commercialized projects: transparent conductive oxide (TCO) for aerosol applications and Roll-to-Roll atomic layer deposition (ALD).
During 2013 alone, Beneq sold three Roll-to-Roll ALD systems. The world’s first scaled-up Roll-to-Roll ALD system was delivered to the Advanced Surface Technology Research Laboratory (ASTRaL), a research unit based in Mikkeli, Finland, that belongs to the Lappeenranta University of Technology. This laboratory has been a global forerunner in developing new applications that take advantage of ALD coatings. The second delivery went to the UK’s Centre for Process Innovation (CPI). The third delivery will go to an undisclosed partner, whose unit is currently in build phase.
“Our Functional Materials program, which focused particularly on coatings and coating technology, achieved excellent results, despite the economically challenging times,” says Markku Lämsä, Program Manager from Tekes. “From the projects completed, we have more than 100 patents, 200 scientific publications and 90 theses. Moreover, companies that participated in the program estimate that they have already received over EUR 60 million in new funding from foreign investors.”
The final seminar of the Functional Materials program, which Tekes carried out from 2007 to 2013, brought together over 300 experts from many different fields. Beneq received its award at the end of the day.
“When we began, we only had a strong belief in our special coating know-how. Yet, we have continued to be driven mostly by our passion to reach a commercialized breakthrough – and bring our coating technologies to real-life applications” says Sampo Ahonen, CEO, Beneq. “We took well-calculated risks to bring something new to the market. But these kinds of decisions always need a strong vision and perseverance. This award validates the tough decisions we made many years ago.”
“I wish to extend my heartfelt thanks to all our Beneq employees, the team at Tekes and all our suppliers and partners. Without them, we would not be here today. A company always needs to rely on talented team members who are ready to give their best to accomplish a challenging goal,” he continues.[as reported by Beneq http://www.beneq.com/news.html#n1]
Press Release May 21, 2013
Gilbert AZ and Dresden, Germany— May 7, 2013 – Arizona-basedColnatec LLC and Fraunhofer Center Nanoelectronic Techologies (IPMS-CNT), of Dresden, Germany, have signed a joint research and development agreement with the mutual goal of advancing the development of deposition equipment and processes for atomic layer deposition (ALD) in semiconductor and photovoltaic applications. The project itself will test the efficacy of Colnatec’s real-time, high-temperature film thickness monitoring system in a manufacturing-scale equipment environment.
Colnatec Engineer on source inspection before final design of chamber feed thru is made.
One of the key issues in ALD is the lack of in-situ process control during production. This is due to the high temperatures and the corrosive nature of the constituent gases used. The lack of real time measurement leads to an inability to control the process, the ramifications of which are yield loss, process failure, and poor production economics.
“Current competitor measurement systems are post production, meaning manufacturers can’t prevent yield loss from precursor pulse failure,” commented Colnatec CEO, Wendy Jameson. “With a real-time system in place inside the hot chamber, process line engineers can know immediately if a pulse failure occurs, as it occurs, and stop the process before the wafer is ruined, saving thousands of dollars per batch.”
“Another potential use for the sensor system is for particulate,” added Scott Grimshaw, Colnatec Chief Technology Officer. “Tempe operates as a machine maintenance sensor, predicting when an ALD system needs to be cleaned. With the minute amounts of “dirt” allowable inside a chamber, having a dirt-buildup warning system is akin to having a smoke detector: as soon as maximum allowable amounts of particulate accumulate, the system shuts off, sending a warning signal to the operator and preventing wafer damage.”
Colnatec hook up to a 300mm Metal PEALD at Fraunhofer IPMS-CNT. The sensor can access the centre of chamber and by stepless movement move out to radius corresponding to 300mm and 450mm (!).
With the scaling down of semiconductor devices, need for nanotechnology has increased tremendously. Nanoscale devices need to be as thin and perfect as possible, so the use of ALD during nanofabrication is inherently well suited, as it is intrinsically atomic in nature and results in the controlled deposition of films at the atomic scale, conformal coatings, and pin-hole free deposition. Today ALD is used in production of DRAM, Advanced CMOS, MEMS, and passivation of crystal silicon solar cells, to name a few applications.
The Tempe™ System is designed for thin film coating process control when high evaporation or chamber temperatures are required. Because it is able to maintain temperatures within a range of 50-500ºC the sensor is able to detect the breakdown of the gases used in the ALD process. This leads to a real-time measurement of film thickness on the order of Angstroms. The Tempe™ system is equally suited for other high temperature manufacturing processes, including thin film solar cell, organic light emitting diode (OLED), chemical vapor deposition (CVD), and rapid thermal processing (RTP). Combined with the Eon™ film thickness controller, which is capable of real-time correction of any natural frequency drift in the crystal during heating, any process that requires heated crystals or high measurement accuracy will see exponential improvement, leading to the highest accuracy possible as well as enabling continuous crystal operation without cooling.
“Colnatec sensors are exciting for us,” noted Dr. Jonas Sundqvist, Group Leader, High-k Devices at Fraunhofer CNT, “because they will give us insight into our process where we’ve had none before. They also enable us to build better ALD equipment, develop stable ALD precursor chemistries, and eventually deliver a process to our customers worthy of mass production with a low cost of ownership. By integrating the Tempe™ sensor in to the ALD process chamber kit,” he added, “we think we can reduce machine down time, use fewer test wafers, and optimize time and fab floor space for ex-situ process control through monitoring with in-line metrology. This could be very important for our industry--today on 300mm wafers but especially for the upcoming move to 450mm wafer size.”Visit Colnatec at http://colnatec.com/
PICS - A EU project to develop innovative Atomic Layer Deposition materials and tools for high density 3D integrated capacitors
GRENOBLE and CAEN, France – Oct. 23, 2013 –CEA-Leti, Fraunhofer CNT and three European SMEs, IPDiA, Picosun and SENTECH Instruments, have launched a project to industrialize 3D integrated capacitors with world-record density.
Thetwo-year EU-funded PICS project is designed to develop a disruptive technology that results in a new worldrecord for integrated capacitor densities (over 500nF/mm2) combined with higher breakdown voltages. It will strengthen the SME partners’ position in several markets, such as automotive, medical and lighting, by offering an even higher integration level and more miniaturization.
The fast development of applications based on smart and miniaturized sensors in aerospace, medical, lighting and automotive domains has increasingly linked requirements of electronic modules to higher integration levels and miniaturization (to increase the functionality combination and complexity within a single package). At the same time, reliability and robustness are required to ensure long operation and placement of the sensors as close as possible to the “hottest” areas for efficient monitoring. For these applications, passive components are no longer commodities. Capacitors are indeed key components in electronic modules, and high-capacitance density is required to optimize – among other performance requirements – power-supply and high decoupling capabilities. Dramatically improved capacitance density also is required because of package shrink.
IPDiA has for many years developed an integrated capacitors technology thatout performs current technologies (e.g. tantalum capacitors) in terms of stability in temperature, voltage, aging and reliability. Now, a technological solution is needed to achieve higher capacitance densities, reduce power consumption and improve reliability. The key enabling technology chosen to bridge this technological gap is atomic layer deposition (ALD) that allows an impressive quality of dielectric.
Picture 1: Prototype of medical pills integrating temperature sensor and RF transceiver
Picture 2: 3D trench capacitors integrated into Silicon
The PICS project consortium will address all related technological challenges and setup a cost-effective industrial solution. Picosun will develop ALD tools adapted to IPDiA’s 3D trench capacitors. SENTECH Instruments will provide a new solution to more accurately etch high-K dielectric materials. CEA-Leti and Fraunhofer CNT will help the SMEs to create innovative technological solutions in order to improve their competitiveness and gain market share. Finally, IPDiA will manage the industrialization of these processes.
Dresden, Germany and Espoo, Finland, October 25, 2013 – Picosun Oy, the leading Atomic Layer Deposition (ALD)equipment manufacturer, provides novel batch ALD processes for fast, cost-efficient mass production of next generation 3D capacitors.
High power density 3D capacitor technology, which is suitable for storing and handling largequantities of energy, is utilized for example in pacemakers and other implantable medical devices, electric cars, and more and more efficient memories for computers and mobile devices. To realize these applications, power consumption, long-term stability, and general reliability of the capacitors and other related electronic components need improvement and their footprint substantial reduction.
Advanced, innovative ALD structures are in a central role when addressing these challenges and Picosun, as the leading supplier of mature batch ALD technology, is a natural choice for providing both ALD tools and processes for the capacitor manufacturing. With its demonstrated, optimized and production-proven ALD processes, Picosun is solidifying its position as the technological leader in the future 3D capacitor market.
“Picosun is the only company offering mature ALD batch equipment that can run stand alone or be clustered using a vacuum robot enabling a production ramp in a cost-efficient way. We aim at transferring our proven high-k capacitor material and process knowledge to an ALD batch system from Picosun and thereby improving cost-of-ownership for applications employing thicker high-k for high voltage applications. Such an offering is not available at the market today,” comments Dr. Jonas Sundqvist, group leader of high-k devices at Fraunhofer CNT, Germany. Fraunhofer CNT, a top European research center for micro- and nanoelectronics is one of Picosun’s collaboration partners in the EU 7th Framework Program project PICS (“Development of innovative ALD materials and tools for high density 3D integrated capacitors”, http://www.fp7-pics.eu/), a part of which the work for the next generation 3D capacitor production upscaling is.
Picosun’s world leading ALD technology enables industrial leap into the future by novel, cuttingedge coating solutions, with four decades of pioneering, groundbreaking expertise in the field. Today, PICOSUN™ ALD systems are in daily production use in numerous prominent industries around the globe. Picosun is based in Finland, it has its subsidiaries in USA and Singapore, and world-wide sales and support network.
[as published on ALDPulse.com] Publication plan for the
virtual project on the history of ALD, v2.0
January 13, 2014
Riikka Puurunen (Dr.), Senior Scientist, VTT Technical Research Centre of Finland
Jonas Sundqvist (Dr.), Group Leader High-k Devices, Fraunhofer IPMS-CNT, Germany
Annina Titoff, editor-in-chief, www.aldpulse.com
The goals of the publication plans are
a) To document early publications about ALD and spread information about them, and b) to promote interaction amongst the ALD Community.
1) Poster at Baltic ALD 2014
The poster will report the literature list and personal comments on the individual publications similarly as collected in the “Google file”, link here. Up to year 1986 will be covered. [The time limit comes from the review of Goodman and Pessa, J. Appl. Phys. 60, R65 (1986), after which ALD literature cannot be considered “early”.]
The poster will have OPEN AUTHORSHIP, meaning that anyone who is interested to contribute in the building of an overview of the early history of ALD, may join the poster.
Each author should provide minimum one comment.
The author list will be alphabetical (basis: last name).
There will be no upper limit for the number of authors: the more authors there are, the better. (Count as of Jan 13, 2014: 23 authors from 9 countries.)
The conference deadline for the poster abstract is January 31. In practice, the abstract will be finalized and submitted a couple of days before that (latest Jan 28).
We will start to finalize the actual poster in the beginning of April. Interested people can still join as authors for the poster at least until March 2014.
2) Listing the early works at the aldpulse.com site
After BALD 2014, the reference list created will be published at the aldpulse.com website.
The list will include the authors, titles translated to English, original titles in the original language (Russian, Finnish, German, ...), and the publication info.
A note will be made somewhere near to the reference list, acknowledging that the list was created in an open and collaborative way in the effort called the “virtual project on the history of ALD”.
The comments made in the Google file will NOT in general be included.
If it appears that it would be useful to include some comments, the permission to do so will be individually sought by the one who made the comment, and the comment will only be included if a clear written acceptance (email or similar) is given.
3) Poster at ALD 2014, Kyoto
The result of the “virtual project on the history of ALD” will be published as a poster also at the AVS-ALD 2014 conference, Kyoto, June 15-18, 2014.
The concept for the poster at ALD 2014 in Kyoto will be similar as for the BALD 2014 poster, both concerning the contents and the OPEN AUTHORSHIP.
The conference deadline for the abstract is February 14. The plan is to submit the abstract on February 10, and interested authors can join until this date.
We will start to finalize the actual poster in the end of May. Interested people can still join as authors for the poster until May 15.
4) Oral(?) presentation at ALD 2014, Kyoto
We will request another presentation at ALD 2014. Oral presentation is preferred, but we will also be happy, if a poster presentation is granted.
The goal is to go one step further in interpretations than in the posters, and to describe the major “new” information found on the early evolution of ALD in the Virtual Project on the History of ALD.
There is OPEN AUTHORSHIP also for this.
The authors are listed in an alphabetical order.
Authors of this presentation should also be authors of the posters (vice versa is not necessary).
If accepted as an oral presentation, the presentation will be given by Riikka. All authors will have a chance to propose contents and give comments on the presentation in advance. Would it be difficult to choose contents, Riikka Puurunen and Jonas Sundqvist will in the end decide what is included in the presentation.
5) A review article on the early history of ALD
The plan is to write a review on the early developments of ALD in a scientific journal. Optionally, we may seek to publish a translation of the review paper also in Russian.
The author list in the review article will be in the alphabetical order.
Prospective authors are requested to contact Riikka Puurunen (riikka.puurunen @vtt.fi), and Jonas Sundqvist (jonas.sundqvist @cnt.fraunhofer.de) and explain how they could contribute to the review article. All authors of the review article should preferably participate also in the poster presentations.
6) Updating wikipedia
If after accomplishing the “virtual project on the history of ALD” and writing the review paper it is evident that the information in wikipedia on the ALD pages can be improved, this will be done. (If you would like to volunteer for this, please contact us.)
Page of “atomic layer deposition”
Page of “atomic layer epitaxy”
Page of “multiple independent discoveries”
January 13, 2014
[From Fraunhofer IPMS-CNT Web www.cnt.fraunhofer.de] The progressive miniaturization of electronic devices such as of smartphones or sensors for medical, industrial and automotive applications requires smaller substrates. This drives amongst others the integration and scaling of space consuming external passive components for buffering and decoupling purposes on chip (SoC) or package (SiP) level. Simultaneously, extremely high capacitances are needed. The main parameters to increase the capacitance are on the one side the choice of an isolator material with high dielectric constant. Several high-k materials like HfO2, ZrO2 or Ta2O5 based systems are under investigation at the Fraunhofer IPMS-CNT .
Intensive material tuning is necessary to meet the electrical requirements for capacitor applications with respect to capacitance density and linearity, leakage current and reliability. While doing this, the capacitor area has to be as large as possible andthat can be achieved by 3D integration of high aspect ratio (AR) structures.
a) SEM cross section of a trench array with AR 13:1 filled with MIM stack and b) top down micrograph of Si trench array after silicon etch.
c) TEM micrograph of a MIM stack
The Fraunhofer IPMS-CNT has developed Si-integrated high-density capacitors based on 300 mm wafer technology aiming to buffer capacitor applications. A simplified patterning scheme using e-beam lithography and high technology dry etch processes provides structures with large aspect ratio in a high package density (Figure 1a and 1b). The used capacitor stack is based on a metalinsulator-metal (MIM) structure built from Al-doped ZrO2 as dielectric and TiN electrodes. All materials are deposited by atomic layer deposition to reach highly conformal step coverage in the large aspect ratio structures (Figure 1c). The electrical characteristics show very low leakage current densities normalized for a capacitor of 1 μF. Thereby, the capacitance is stable over the voltage region with a deviation smaller than 3 %.
The temperature stability is below 5 %. These values are significantly lower compared to common ceramic capacitors. The good electrical results are complemented by a reliability over 10 years. The maximum capacitance reached for the AR of 6:1 (Gen2) lies around 100 nF/mm2 for the material system which is adapted to an operation voltage of 3 V. This is a significant increase compared to planar capacitors (Gen1).. By increasing the AR to 13:1 (Gen3) a capacitance enhancement to 220 nF/mm2 could be achieved.
The Fraunhofer IPMS-CNT forces also an up-scaling of the 3D capacitors (Gen4-5) either by an improved etch-process or by using materials with higher dielectric constant. The outlook predicts integrated capacitors of 1 μF.
Further Information can be find in this excellent pape by Wenke Weinreich et al
Housing leading-edge technology derived from Colnatec’s Eon™ frequency-temperature compensating circuitry, the Millennium™ Controller is an ultra-high resolution thin film deposition control system packaged into a standard 19-inch rackmount enclosure and featuring a versatile touch screen display.
Incorporating the same technology as the Eon-LT™, the Millennium™ offers a temperature measuring film thickness controller built into a modular framework. The Millennium™ controller, which is designed with the same level of dependability and precision of all Colnatec products, supports up to four sources and sensors (2 standard), co-deposition functionality, real-time frequency-temperature curve generation, and 500°C crystal operation.Here are all the details: LINK
Researchers at the Swiss Federal Institute of Technology in Zurich (ETH Zurich) have created clear, flexible electronic circuitry that is so thin it can sit upon the surface of a contact lens, or be wrapped around a human hair according to Gizmag.com. The research, led by Dr. Giovanni Salvatore, could ultimately be used for implantable medical devices. One such potential application suggested by the team is a “smart contact lens” that could monitor intraocular pressure for glaucoma patients.
In order to create the circuits, the layers are deposited using e-beam evaporation, atomic layer deposition, spin coating and radio frequency sputtering. The structuring is created using ultraviolet (UV) lithography and etching. The circuits are created on a substance called parylene, an insulator that is traditionally used as a protective coating for electronic devices and components.
Online Abstract Submission Open : December 2, 2013
Deadline for Abstract Submission : January 31, 2014
Online Registration and Hotel Accommodation Open : January 1, 2014
Notification of Acceptance : March 15, 2014
Deadline for Online Registration : April 17, 2014
NB! The abstract submission deadline has been extended by one week till February 7, 2014
Hörsaal TU Dresden Fakultät Informatik: http://www.inf.tu-dresden.de/index.php?node_id=12&ln=de
Nöthnitzer Straße 46 D-01187 Dresden
(between Namlab and the MPI last year)
Preliminary Program for the Workshop coming soon
Fraunhofer IPMS-CNT cordially invite to "Nanoelectronic Technologies for Future Smart Systems" in Dresden. This time with high-level speakers from Globalfoundries, IBM, Infineon, IMEC and JSR Mirco. Full program and online registration behind the link.
Get Together & CNT Clean Room Window Tour (limited capacity!)
8:30 a.m. -Registration-
9:00 a.m. WelcomeProf. Dr. Hubert Lakner, Director Fraunhofer IPMS, Chairman Fraunhofer Group Microelectronics
9:15 a.m. Cooperation is Key - R&D perspectives at Globalfoundries Dresden, Dr. Manfred Horstmann, Director Technology & Integration, Device - Globalfoundries
9:45 a.m. Made in Dresden - Infineon Today & Tomorrow, Dr. Norbert Thyssen, Director Customer Services / Dvmt. Projects - Infineon
10:15 a.m. Coffee Break
Session: Devices in Back-End-of-Line
10:40 a.m.Challenges for 28 nm BEOL, Thomas Werner, Manager Technology & Integration Engineering - Globalfoundries
11:05 a.m. Chemical screening for CMP applications, Peter Bridger, CMP Project Manager - JSR Micro, Belgium
11:30 a.m. CNT as test bed for chemical screening, Dr. Benjamin Uhlig, Fraunhofer IPMS-CNT Interconnects
11:55 a.m. High-k 3DMIM-Cap Devices, Dr. Wenke Weinreich, Fraunhofer IPMS-CNT High-k Devices
12:20 p.m.-Lunch Break-
Session: Logic & Memory Scaling
1:00 p.m. New front-end materials for continued CMOS logic scaling, Dr. Martin M. Frank, BM Research/New York
1:25 p.m. RRAM - Challenges and Opportunities of an Emerging Memory, Dr. Malgorzata Jurczak, Director Emerging Memory Devices - IMEC Belgium
1:50 p.m. A CMOS-compatible and highly scalable approach to future ferroelectric memories, Johannes Müller, FraunhoferIPMS-CNT High-k Devices)
2:15 p.m. -Short Coffee Break-
Session: MEMS, Passives & Nanopatterning
2:25 p.m. Nanopatterning using alternative Litho, Dr. Christoph Hohle, Fraunhofer IPMS-CNT Nanopatterning
2:50 p.m. MEMS-Technology at Fraunhofer IPMS, Dr. Michael Müller, IPMS MEMS Sensors)
3:15 p.m. -End of Program-
Good news for everybody seaking to go to Japan this summer and attend the ALD 2014. The website for the AVS-ALD 2014 conference is now open, and a first call for papers has been issued. Check it out here: http://www.ald2014.org/
Also a twitter account ALD 2014 @ALD_2014 has come alive. Nice!
Delphine Longrie, Davy Deduytsche and Christophe Detavernier
J. Vac. Sci. Technol. A 32, 010802 (2014)
"The Global Atomic Layer Deposition Market 2014-2018, has been prepared based on an in-depth market analysis with inputs from industry experts. The report covers the Americas, the EMEA region, and the APAC region; it also covers the Global Atomic Layer Deposition market landscape and its growth prospects in the coming years. The report also includes a discussion of the key vendors operating in this market."
Analysts forecast the Global Atomic Layer Deposition market to grow at a CAGR of 36.10 percent over the period 2013-2018. According to the report, growing demand for miniaturized components is one of the major drivers of the Global ALD market. With the rapid development of nanotechnology and other advanced technologies, several manufacturing companies are in the process of manufacturing nano-components for increased compatibility and greater efficiency. Therefore, manufacturing companies across industries prefer the ALD technique to manufacture several smaller components.
Further, the report states that one of the major challenges is the need for high levels of investment. ALD equipment and materials are priced at a premium, hindering their adoption among SMEs.
Global Atomic Layer Deposition Market 2014-2018, has been prepared based on an in-depth market analysis with inputs from industry experts. The report covers the Americas, the EMEA region, and the APAC region; it also covers the Global Atomic Layer Deposition market landscape and its growth prospects in the coming years. The report also includes a discussion of the key vendors operating in this market.
The report recognizes the following companies as the key players in the Global Atomic Layer Deposition Market: Adeka Corp., Applied Materials Inc., and ASM International N.V.
Other vendors mentioned in the report are Air Liquide S.A., Air Products and Chemicals Inc., AIXTRON SE, Arradiance Inc., ATMI Inc., Beneq Oy, Centrotherm Photovoltaics AG, Encapsulix SAS, Hitachi Kokusai Electric Inc., Kurt J. Lesker Co., Levitech BV, NCD Co. Ltd., Nova-Kem LLC., Oxford Instruments plc, Picosun Oy, Praxair Technology Inc., SENTECH Instruments GmbH, SoLayTec, Strem Chemicals Inc., SVT Associates Inc., Tokyo Electron Ltd., Tosoh Corp., Ultratech Inc., and Veeco Instruments Inc."
01. Executive Summary
02. List of Abbreviations
03. Scope of the Report
03.1 Market Overview
03.2 Product Offerings
04. Market Research Methodology
04.1 Market Research Process
04.2 Research Methodology
06. Market Landscape
06.1 Market Overview
06.2 Market Size and Forecast
06.3 Five Forces Analysis
07. Market Segmentation by Product
07.1 Equipment Segment
07.1.1 Market Size and Forecast
07.2 Materials Segment
07.2.1 Market Size and Forecast
08. Market Segmentation by End-users
09. Market Segmentation by Application
10. Geographical Segmentation
10.1.1 Market Size and Forecast
10.2 EMEA Region
10.2.1 Market Size and Forecast
10.3 APAC Region
10.3.1 Market Size and Forecast
11. Buying Criteria
12. Market Growth Drivers
13. Drivers and their Impact
14. Market Challenges
15. Impact of Drivers and Challenges
16. Market Trends
17. Trends and their Impact
18. Vendor Landscape
18.1 Competitive Scenario
18.1.1 Key News
18.1.2 Mergers and Acquisitions.
18.2 Major Vendor Analysis
18.3 Other Prominent Vendors
18.3.1 ALD Equipment Vendors
18.3.2 ALD Precursor Vendors
19. Key Vendor Analysis
19.1 Adeka Corp.
19.1.1 Business Overview
19.1.2 Business Segments
19.1.3 Key Information
19.1.4 SWOT Analysis
19.2 Applied Materials Inc.
19.2.1 Business Overview
19.2.2 Business Segments
19.2.3 Key Information
19.2.4 SWOT Analysis
19.3 ASM International N.V.
20. Other Reports in this Series
List of Exhibits:
Exhibit 1: Market Research Methodology
Exhibit 2: Global ALD Market 2013-2018 (US$ million)
Exhibit 3: Global ALD Market by Product Segmentation 2013-2018
Exhibit 4: Global ALD Market by Equipment Market 2013-2018 (US$ million)
Exhibit 5: Global ALD Market by Materials Market 2013-2018 (US$ million)
Exhibit 6: Global ALD Market by End-user Segmentation 2013
Exhibit 7: Global ALD market by Geographical Segmentation 2013-2018
Exhibit 8: ALD market in the Americas 2013-2018 (US$ million)
Exhibit 9: ALD market in the EMEA Region 2013-2018 (US$ million)
Exhibit 10: ALD market in the AAPC Region 2013-2018 (US$ million)
Exhibit 11: Business Segments of Adeka Corp.
Exhibit 12: Business Segments of Applied Materials Inc."